Higher speed semiconductor devices may be achieved by reducing parasitic capacitances. A typical metal-oxide-semiconductor field-effect transistor (MOSFET) transistor is fabricated on a silicon substrate or within a well in the substrate, and has a large parasitic capacitance to this substrate or well.
Silicon-On-Insulator (SOI) processes eliminate the substrate or well, replacing it with an insulator layer such as a buried oxide. The transistor source, drain, and channel typically are formed on top of the buried oxide so that there is little or no parasitic capacitance to the substrate. Thus SOI devices may achieve much higher operating speeds than traditional silicon processes.
However, the extremely tiny transistors have a thin gate oxide that can be damaged by relatively small currents with even a moderate driving force (voltage). Special care is required when a human handles these semiconductor devices.
Static electricity that normally builds up on a person can discharge across any pair of pins of a semiconductor integrated circuit (IC or chip). IC chips are routinely tested for resistance to such electrostatic discharges (ESD) using automated testers that apply a Human-Body Model (HBM) current pulse across different pairs of pins of the chip. Any pair of pins may be chosen for the ESD test.
In a power clamp, large transistors with gate widths of 1,000 to 5,000 μm have been used for protection. Such large transistors are usually a Field-Effect Transistor (FET) and are referred to as a BigFET.
FIG. 1 shows a prior art power-to-ground ESD protection circuit with an active R-C triggered BigFET power clamp.
An R-C sensing element is formed by capacitor 22 and resistor 20. Inverters 10, 12, 14 invert the sensed voltage between capacitor 22 and resistor 20, and drive the gate of n-channel power clamp BigFET 18.
Under normal conditions, resistor 20 drives the input of inverter 10 high, causing a low to be driven onto the gate of n-channel BigFET 18, keeping it off. When the power-to-ground voltage suddenly spikes high, such as during a positive ESD event, capacitor 22 keeps the input of inverter 10 low for a period of time determined by the R-C time constant. The low input to inverter 10 drives the gate of n-channel BigFET 18 high, turning on n-channel BigFET 18 and shunting current from power to ground, dissipating the ESD pulse applied to the power line. After the R-C time period has elapsed, resistor 20 pulls the input to inverter 10 high, and a low is driven onto the gate of n-channel BigFET 18, turning it off.
Sometimes the polarity of the ESD pulse is reversed. A positive pulse may be applied to ground, while VDD is grounded. N-channel BigFET 18 might not turn on for such a negative pulse. However, when n-channel BigFET 18 is formed with a typical silicon process, parasitic substrate diode 19 also exists due to the source/drain-to-substrate p-n junctions under n-channel BigFET 18. Since n-channel BigFET 18 is a physically large device, parasitic substrate diode 19 is also a large device that can carry the large ESD currents. The positive ESD pulse applied to ground is shunted through parasitic substrate diode 19 to VDD, rather than through n-channel BigFET 18.
FIG. 2 is a cross-section of a BigFET ESD protection device using a typical silicon process. P-well 50 is formed in n-substrate 56, and source/drain/tap regions are formed by openings in field oxide 54. N+ regions 42, 44, 48 and P+ region 46 are formed in P-well 50.
Parasitic substrate diode 19 is formed by P-well 50 and N+ region 42. Gate 52 with gate oxide 60 form n-channel BigFET 18 that conduct between N+ region 42 and N+ region 44 when a positive ESD pulse is applied to terminal A and terminal B is grounded. However, when the positive ESD pulse is applied to terminal B and terminal A is grounded, n-channel BigFET 18 may remain off. Instead, parasitic substrate diode 19 is forward biased and conducts the ESD pulse from terminal B, through P+ region 46 that taps P-Well 50, across the pn junction to N+ region 42, and out to grounded terminal A.
Although circuit designers may believe that n-channel BigFET 18 is providing protection, parasitic substrate diode 19 may actually be conducting for negative ESD pulses. Parasitic substrate diode 19 may be left out of circuit schematics, but it is still present when a typical silicon process is used.
ESD protection circuits that work for typical silicon processes may fail when migrated to Silicon-On-Insulator (SOI) processes. SOI processes lack parasitic substrate diode 19. Current can no longer be shunted through parasitic substrate diode 19 since it does not exist on a SOI process.
FIG. 3 is a cross-section of a BigFET ESD protection device on a SOI process. Buried oxide 62 is a layer formed on top of substrate 56. Substrate 56 could be a silicon substrate or could be a sapphire or other substrate. Buried oxide 62 isolates substrate 56 from N+ regions 42, 44 and channel region 64 formed under gate 52 and gate oxide 60 in n-channel BigFET 18 (FIG. 1). It is not possible for ESD current from terminal B to pass from N+ region 44 through substrate 56 to N+ region 42 and terminal A, since Buried oxide 62 blocks all current flow to substrate 56. Thus parasitic substrate diode 19 is not present.
In a standard SOI process, N+ regions 42, 44 are formed on top of buried oxide 62. Field oxide 54 isolates each SOI transistor from its neighbors. Channel region 64 is a silicon region that has an opposite doping from the source/drain regions, such as p-type for an NMOS transistor. In a floating body SOI process a thin conducting channel region forms under gate oxide 60 when gate 52 is at a high voltage. This conducting channel has an opposite polarity of electric carriers than does the channel region itself, so the conducting channel is known as an inversion layer. A non-conducting depletion region may form under the channel in channel region 64 while the remainder of channel region 64 is not depleted. In a SOI fully depleted device, all of channel region 64 is depleted, rather than just the top of channel region 64. Gate oxide 60 could be a thin gate oxide or could be a thicker oxide for n-channel BigFET 18.
FIG. 4 shows a SOI FIN-FET device. Another variation of SOI processes produces a FIN-FET device. N+ regions 42, 44 are still formed on top of buried oxide 62, but N+ regions 42, 44 are very thin, having a fin-like appearance. Between N+ region 42 and N+ region 44 is a connecting region of lightly-p-doped silicon that acts as the transistor channel. N+ region 42, the channel connecting region, and N+ region 44 can all be formed on the same fin of silicon.
Gate 52 is formed around the channel connecting region. Rather than being flat, gate 52 has an inverted U-shape that surrounds the channel connecting region between N+ regions 42, 44. As gate oxide 60 is formed on three sides of the fin-like channel connecting region rather than only on the top surface of the channel region.
FIN-FET transistors may have better current drive than equivalent flat transistors for the same die area due to this 3-D gate and channel structure. However, buried oxide 62 prevents formation of parasitic substrate diode 19. ESD protection devices cannot rely on parasitic substrate diode 19 when SOI or FIN-FET processes are used.
Some SOI ESD protection devices add a shunt diode across n-channel BigFET 18. However, this added shunt diode must carry a large current and thus has a large area and cost.
Other SOI ESD protection circuits may not provide full rail protection, where the ESD pulse may be applied to any pair of pins, and the internal VDD and ground rails in the chip are used to route the ESD current. However, the internal circuits might be easily damaged.
What is desired is an ESD-protection circuit that uses SOI transistors without a parasitic substrate diode. An ESD-protection circuit for SOI that provides full ESD protection for any ESD zapping combination of pins is desirable. An SOI ESD-protection circuit that does not have a large shunt diode is desirable. Rail-based and pad-based full-chip protection with a SOI ESD-protection circuit that does not have a large shunt diode is desired.